Thermo-Mechanical Reliability Analysis of Through-Silicon-Via (TSV)
Application ID: 131101
Through-silicon vias (TSVs) allow chips or wafers to be connected vertically, making TSV a crucial technology for 2.5D and 3D packaging. The basic structure of a TSV consists of a deep hole penetrating a silicon substrate, a filling metal (usually copper) in the deep hole, and an insulating layer between the metal and substrate. The temperature fluctuation during the manufacturing process of a TSV as well as the operation of the device may introduce thermal stress in the structure and cause the copper filling to protrude or descend. This stress may also cause plastic deformation of the copper and even slippage or cracking at the copper-silicon interface, which could affect the electrical connection performance of the TSV and cause the failure of devices.
In this model, the thermomechanical reliability of a single TSV is analyzed, taking into consideration the thermal stress and the plastic deformation of copper. The deformation and stress results can be used to determine the range of the keep-out zone (KOZ) around the TSV, an area where the components with electrical functions should avoid.
This model example illustrates applications of this type that would nominally be built using the following products:
however, additional products may be required to completely define and model it. Furthermore, this example may also be defined and modeled using components from the following product combinations:
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