Phase Delay of a SOI Tapered Waveguide
Application ID: 151161
A small building block of integrated photonics, i.e., a Silicon-on-Insulator taper, is considered. For a larger system design, it might be useful to determine the phase delay such a device introduces.
Here, we showcase the layout needed to do it in COMSOL, including a proper Port placement, its phase correction, and manual phase extraction.
We also touch on the way a 3D Frequency Domain simulation correlates with a 2D Boundary Mode Analysis and analytic Transfer Matrix Method considerations. This also provides us with an option to validate the finite element model.
This model example illustrates applications of this type that would nominally be built using the following products:
however, additional products may be required to completely define and model it. Furthermore, this example may also be defined and modeled using components from the following product combinations:
The combination of COMSOL® products required to model your application depends on several factors and may include boundary conditions, material properties, physics interfaces, and part libraries. Particular functionality may be common to several products. To determine the right combination of products for your modeling needs, review the Tabella delle Funzionalità and make use of a free evaluation license. The COMSOL Sales and Support teams are available for answering any questions you may have regarding this.
