Geometry Induced Electric Field Enhancement in PCB under ESD Stress
Printed circuit boards (PCBs) incorporating a single layer of copper traces are commonly used to route power and signals to light-emitting diodes (LED). These boards were evaluated using the 15 kV air discharge test in according to IEC 61000-4-2 Electromagnetic compatibility (EMC) - Part 4-2: Testing and measurement techniques - Electrostatic discharge immunity test. Testing revealed ESD-induced damage concentrated near a specific region of the copper traces.
To investigate the failure mechanism, finite element simulations were performed using COMSOL Electrostatics module to model the electric field distribution on the PCB when subject to 15 kV. Electric field strengths at multiple locations along the traces were compared to identify regions experiencing enhanced electric field. The simulation showed that the highest electric field strength occurred at trace corners, consistent with the observed locations of the ESD damage.
The COMSOL simulation was subsequently used to evaluate alternative trace geometries and their corresponding electric field distributions. Based on these results, an improved trace design was developed to reduce field concentration at critical locations. The revised design reduced the device failure rate and improved ESD immunity.
